The present disclosure relates to integrated memory circuits, and in particular, to an apparatus and method for wordline voltage compensation in integrated memory circuits.
In a typical computing system, a memory hierarchy supports a central processing unit (xe2x80x9cCPUxe2x80x9d) with data storage capabilities. Generally, the type of memory device used as the primary random access memory (xe2x80x9cRAMxe2x80x9d) in a computing system is dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). DRAM is comparatively low in cost and high in density, facilitating the storage of large quantities of data within a small volume of the computing system.
Each DRAM is typically organized into memory arrays or banks, with each memory bank having a corresponding sense amplifier (xe2x80x9cSAxe2x80x9d). Data refresh is typically accomplished by accessing each row in each memory bank, one row at a time. When the memory banks are accessed to be refreshed, data stored in the memory cells of the banks are read to the sense amplifiers, and immediately written; back to the memory cells. A capacitor corresponding to each memory cell is thus recharged to its initial value.
Wordlines are used to access a memory cell within a row for refresh and non-refresh read and write operations. Generally in the design of DRAM, the magnitude of the wordline on or high voltage (xe2x80x9cVPPxe2x80x9d) is a major component of the rate with which charge is transferred into and out of the array storage cell in both the read and write modes of operation. This rate of charge transfer limits critical timing parameters such as write-back and the Row to Column delay (xe2x80x9cTrcdxe2x80x9d), or, in the case of SDRAMs, the Open Bank to Read/Write Command. Thus, it is desirable to have this voltage be as high as the device reliability allows. The wordline off or low voltage (xe2x80x9cVWLLxe2x80x9d) is also a key parameter, strongly influencing the transfer device""s off current (xe2x80x9cIOFFxe2x80x9d), and as a consequence, cell retention time. In some DRAM designs, this is a negative voltage generated on the chip. For these designs it is desirable to make this voltage as negative as possible while not exceeding the maximum voltage stress that is the sum of the absolute values of the wordline off voltage and the wordline on voltage.
Traditionally, DRAMs have set the wordline on voltage as high as the reliability requirements will allow, thus generating the highest possible on current for signal development and write-back. However, this voltage does not track the array device threshold voltage (xe2x80x9cVTxe2x80x9d), consequently the transfer device current will vary around its target, on some parts exceeding its target and on other parts falling short. In cases with the fixed wordline voltage approach of the prior art, the array transfer device on all parts is stressed at the maximum allowable voltage. In addition, power consumption to generate the wordline on voltage is fixed at a maximum by the high wordline voltage (xe2x80x9cVPPxe2x80x9d).
On some contemporary DRAM designs, the introduction of a negative wordline off voltage creates an analogous situation to the wordline on voltage. For these designs, the value of the wordline off voltage is chosen to set the desired Ioff current under worst-case process conditions. As with the wordline on voltage, the wordline off voltage does not track the array devices VT, consequently Ioff current will exceed or fall short of a worst-case goal. The voltage stress level and power requirements are also fixed at a maximum expectable level.
For example, the maximum nominal wordline off voltage may be xe2x88x920.5 v and the on voltage 2.6 v, giving a nominal maximum stress voltage of 3.1 v. It is desirable to increase the wordline on voltage (e.g., greater than 2.6 v) for performance and decrease the wordline off voltage (e.g., less than xe2x88x920.5 v) for retention. However, since the maximum difference or delta is 3.1 v, both voltages cannot be increased simultaneously. Unfortunately, power supply references move such that VPP increases as VWLL increases in magnitude, and vise versa, thus increasing or decreasing the voltage swing while not closely tracking process variations that affect device on or off current. As a result, VPP and VWLL are moving independently of array VT and process variations, which causes the need for higher array device Ion current and/or lower array device Ioff current.
These and other drawbacks and disadvantages of the prior art are addressed by an apparatus and method for wordline voltage compensation in integrated memory circuits.
The apparatus is an integrated memory circuit including an array threshold voltage (xe2x80x9cVTxe2x80x9d) monitor, a wordline on voltage (xe2x80x9cVPPxe2x80x9d) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (xe2x80x9cVWLLxe2x80x9d) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage.
The corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.